Figure 1. FBI Plot of Single Bunch Coalescing

As another way of increasing luminosity the Tevatron is moving to operations using more coalesced bunches (36 on 36 vs. 6 on 6). To accomplish this, multiple batches will be coalesced in the Main Ring simultaneously for injection into the Tevatron. This multi-batch operation involves coalescing up to 12 proton or 4 antiproton (pbar) batches at one time. In support of the new multi-batch

coalescing takes place. In this case not all the beam has been recaptured in the central bunch as is seen by the difference between the wide (M:P1IWG) and narrow (M:P1ING) gate plots.

SYSTEM HARDWARE

The system is VME based using an embedded controller with an ethernet interface to the accelerator control system. The hardware consists of a timer board (VRFT), a Tevatron clock decoder (VUCD), two digitizers (Omnibyte Comet) and two gated integrator modules along with the embedded processor (Motorola MVME-162LX) in a modified Tracewell VME chassis. A block diagram of the system is shown in figure 2. While most of the system hardware is either commercial or Fermilab AD/Controls general purpose modules, the dual channel gated integrator modules were specifically designed for this project. This was due to the high speed requirements of the analog processing. The integrator circuit needed to be capable of being gated with integrate windows as short as 18.8 nS with 2 nS maximum rise and fall times, cleared with reset pulses of 50 nS and be ready to integrate again all within 384 nS. This module is described below.
The Resistive Wall Current Monitor is a wideband (2 GHz), AC coupled, low impedance ( .16 ohms) beam current detector. A full description of these types of detectors can be found in reference 1.

Resistive Wall
Monitor

Ethernet
TCLK

To SBD

Main Ring RF

The Motorola MVME-162LX is a standard configuration 68040 based single board VME computer. It serves as the system network (ACNET) interface via its ethernet connection and as the VME bus master. It is configured with VxWorks (Wind River Systems) as its operating system. Software programming is performed in "C" and is downloaded via the network. The MVME-162 has 4 MByte of DRAM and 128K of battery backed RAM which is used to store system settings.
The VUCD and VRFT are standard AD/Controls VME clock decoder boards. The VUCD provides Tevatron clock decoding in order to support plotting and datalogging while the VRFT uses Main Ring RF (53 MHz) and a beam sync marker to generate the system data acquisition gates.
The Omnibyte Comet VME A/D board is a 12 bit, 5MS/s VME digitizer with 64 Kword/channel of memory depth and an external trigger. Two channels (0,1) on each board are used to sample the wide and narrow gate integrated intensities based on an external trigger.

Dual High Speed Integrator

The dual high speed integrator board (figure 3) is a two channel fast gated integrator circuit in a 6U VME form factor. The channels can be configured with jumpers to be either fully independent or have common signal or common trigger

Trigger
Input
CH 1

FIGURE 4. FBI Switch Driver Schematic

inputs. For the FBI each board is configured for a common input but independent

scale RMS noise. The rise and fall time of the switches provide ±.5% amplitude accuracy through a 15 nS window for the 18.8 nS wide gate.
Because the resistive wall monitor used for the FBI is AC coupled, the baseline varies depending on bunch intensities and spacing. With 12 bunches spaced by 21 RF buckets, the baseline is estimated to change by ±.1% between turns. To correct for this, and remove constant integrator errors, the baseline is measured every other turn and subtracted from the measured intensities in software. The accuracy of this procedure depends on the distribution of bunches and where the baseline is sampled.

SYSTEM SOFTWARE

The system software is a compiled C program running in the VxWorks operating system of the embedded processor. It performs all data handling, reading the digitizers, sorting data and performing the proton and pbar summations. Data display is provided via standard control system Fast Time and Snapshot Plots, parameter pages or a local terminal.

Embedded Processor Application

A compiled C program running on the embedded processor performs high speed data transfer across the VME back plane along with sorting and summing of the transferred data. The system reads a complete data set when a data request has been issued. The integrated intensities of the 12 proton bunches are digitized by the proton Comet board as gated externally by the VRFT. The intensity data is interleaved (P1-P11 odd, P2-P12 even) in the digitizer FIFO memory. Channel 0

P1

P2

P3

P4

FIGURE 5. FBI system timing for bunches P1-P4

Console Control

The ability to change the 12 proton gate delays, the 4 pbar gate delays, the proton and pbar zero sample times, as well as the proton and pbar wide gate widths is provided via a console page application. Bunch delay timing for the

easy to use and easy to maintain system for real time individual bunch intensity monitoring.

ACKNOWLEDGEMENTS

We would like to thank J. Crisp for his assistance with the design and analysis of the high speed gated integrator, C. Briegel for his assistance with the embedded processor software and S. Moua for his assistance in assembling the system.

REFERENCES

1.Webber, R.C., "Longitudinal Emittance: An Introduction to the Concept and Survey of Measurement Techniques Including Design of a Wall Current Monitor," AIP Conference Proceedings No.212, pp. 85-126.
2.Utterback, J., and Vogel, G., "Fast Bunch Integrator, A System for Measuring Bunch Intensities in Fermilab's Main Ring," presented at ICALEPCS 95, Chicago, IL, October 29,1995. 3.Wang, X., "Ultrafast, High Precision Gated Integrator," AIP Conference Proceedings No.333, 1994, pp. 260-266.